发明名称 |
Tracking circuit for reducing faults in a memory |
摘要 |
A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line. |
申请公布号 |
US8125842(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US20090415248 |
申请日期 |
2009.03.31 |
申请人 |
DUDECK DENNIS E.;EVANS DONALD ALBERT;PHAM HAI QUANG;WERNER WAYNE E.;WOZNIAK RONALD JAMES;AGERE SYSTEMS INC. |
发明人 |
DUDECK DENNIS E.;EVANS DONALD ALBERT;PHAM HAI QUANG;WERNER WAYNE E.;WOZNIAK RONALD JAMES |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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