| 摘要 |
A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1<VR2, . . . , <VRm<VRm+1, a differential amplifier series including (m+1) differential amplifiers A1-Am+1 configured to amplify voltage differences between the reference voltages VR1-VRm+1 and an input signal voltage, and an operation circuit including a plurality of comparator circuits configured to receive output voltage sets generated by the respective differential amplifiers. The number of comparator circuits varies depending on the value k of the reference voltage VRk, where k is an integer of 2≰k≰m+1.
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