| 摘要 |
An integrated circuit 2 including multiple instances 6, 8, 10, 12 of identical processing circuitry may be modelled within a field programmable gate array integrated circuit 22 by second processing circuitry 28 connected via a multiplexer 26 to first processing circuitry 24 and operating at a multiple of the clock frequency of the first processing circuitry. Demultiplexing circuitry 32 is used to reform the multiple outputs of the respective separate instances to be fed back to the first processing circuitry 24.
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