| 摘要 |
A display data receiving circuit of the present invention includes a PLL circuit 25 which generates internal clock signal ICLK having an integral multiple of the frequency of differential clock signals CLK and /CLK in response to differential clock signals CLK and /CLK, and a serial/parallel conversion circuit 23 which receives serial data signal transmitting display data in synchronization with the internal clock signal ICLK, and generates parallel data signal by executing serial/parallel conversion for the serial data signal. The serial/parallel conversion circuit 23 is configured to be able to execute either a single edge operation, which receives serial data signals in response to one of a rising edge and a falling edge of the internal clock signal ICLK, or a double edge operation, which receives serial data signals in response to both of a rising edge and a falling edge of the internal clock signal ICLK. Further, the PLL circuit 25 is configured to be able to change the frequency of the internal clock signal ICLK. |
