| 摘要 |
One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods. |
