| 摘要 |
Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer.
|
