3D NAND array architecture

摘要

Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).

主权项

1. A memory device on a substrate, comprising:
a multilevel stack of conductive layers, each of the layers being oriented parallel to the substrate; a plurality of pillars oriented orthogonally to the substrate, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers; a plurality of string select lines oriented parallel to the substrate and above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective select gate of the pillar, and all of the string select lines in the plurality overlying a single one of the conductive layers; and a plurality of parallel bit line conductors in a layer parallel to the substrate and above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, the bit line conductors in the plurality having a pitch pBL, each of the pillars underlying one of the bit line conductors, none of the bit line conductors in the plurality of bit line conductors intersecting more than one of the pillars which underlie a single one of the string select lines, wherein the pillars in the plurality of pillars are arranged on a regular grid having two lateral dimensions, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, and all intersecting a single one of the string select lines,
pillar B being a pillar which is nearest to pillar A in the grid,and pillar C being a pillar which is non-collinear with pillars A and B but which is otherwise nearest pillar A in the grid, wherein two adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL), α being the area of the unit cell.