发明名称 Semiconductor memory device capable of compensating variation with time of program voltage
摘要 A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase.
申请公布号 US8102719(B2) 申请公布日期 2012.01.24
申请号 US20100683022 申请日期 2010.01.06
申请人 WATANABE YOSHIHISA;KABUSHIKI KAISHA TOSHIBA 发明人 WATANABE YOSHIHISA
分类号 G11C16/10 主分类号 G11C16/10
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