发明名称 Dense Nanoscale Logic Circuitry
摘要 One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
申请公布号 US2012001653(A1) 申请公布日期 2012.01.05
申请号 US200913256234 申请日期 2009.04.30
申请人 STRUKOV DMITRI BORISOVICH;KUEKES PHILIP J. 发明人 STRUKOV DMITRI BORISOVICH;KUEKES PHILIP J.
分类号 H03K19/173;B82Y99/00 主分类号 H03K19/173
代理机构 代理人
主权项
地址