| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a cache controller capable of reducing a processing load by a processor when discarding cache data in the cache controller. <P>SOLUTION: If it is determined that an access from a master meets a condition of an invalidation range setting unit 121, a cache controller 110 forcibly resets a VALID flag 113 of a corresponding address in a tag memory 111 through an invalidation determination circuit 120 and a tag memory modification unit 122. Thus, cache data of the corresponding address whose VALID flag is reset is discarded without being written back to the memory 104. Then, the data accessed by the master is overwritten in accordance with the corresponding address. <P>COPYRIGHT: (C)2012,JPO&INPIT |
