发明名称 |
CLOCK SYNTHESIS SYSTEMS, CIRCUITS AND METHODS |
摘要 |
A clock synthesis system may include a feed forward divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronous pulse; a modulator that modulates the select signal in response to at least a difference value; a multiplier circuit that frequency multiplies the reference clock to generate an output clock; and a timing circuit that generates the difference value in response to the source clock and synchronous pulse. |
申请公布号 |
WO2011103602(A3) |
申请公布日期 |
2011.12.01 |
申请号 |
WO2011US25780 |
申请日期 |
2011.02.22 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION;CASTOR-PERRY, KENDALL |
发明人 |
CASTOR-PERRY, KENDALL |
分类号 |
H03L7/183;H03L7/08 |
主分类号 |
H03L7/183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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