发明名称 DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
摘要 Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request.
申请公布号 US2011289279(A1) 申请公布日期 2011.11.24
申请号 US201113192104 申请日期 2011.07.27
申请人 SONNIER DAVID P.;BROWN DAVID A.;PEET, JR. CHARLES EDWARD;LSI CORPORATION 发明人 SONNIER DAVID P.;BROWN DAVID A.;PEET, JR. CHARLES EDWARD
分类号 G06F12/08 主分类号 G06F12/08
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