发明名称 |
TECHNIQUES FOR ACCELERATING COMPUTATIONS USING FIELD PROGRAMMABLE GATE ARRAY PROCESSORS |
摘要 |
<p>Various embodiments are disclosed for accelerating computations using field programmable gate arrays (FPGA). Various tree traversal techniques, architectures, and hardware implementations are disclosed. Various disclosed embodiments comprise hybrid architectures comprising a central processing unit (CPU), a graphics processor unit (GPU), a field programmable gate array (FPGA), and variations.or combinations thereof, to implement raytracing techniques. Additional disclosed embodiments comprise depth-breadth search tree tracing techniques, blocking tree branch traversal techniques to avoid data explosion, compact data structure representations for ray and node representations, and multiplexed processing of multiple rays in a programming element (PE) to leverage pipeline bubble.</p> |
申请公布号 |
WO2011142723(A1) |
申请公布日期 |
2011.11.17 |
申请号 |
WO2011SG00182 |
申请日期 |
2011.05.11 |
申请人 |
PROGENIQ PTE LTD;GOVINDARAJAN, SUNDAR;IYER, VINOD RANGANATHAN;DARRAN, NATHAN |
发明人 |
GOVINDARAJAN, SUNDAR;IYER, VINOD RANGANATHAN;DARRAN, NATHAN |
分类号 |
G06T17/00;G06T15/00 |
主分类号 |
G06T17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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