发明名称 |
Method for reducing chip warpage |
摘要 |
A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.
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申请公布号 |
US8053336(B2) |
申请公布日期 |
2011.11.08 |
申请号 |
US20090610873 |
申请日期 |
2009.11.02 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
WU TING-HAU;CHENG CHUN-REN;LEE JIOU-KANG;TSAI SHANG-YING;PENG JUNG-HUEI |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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