| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit for suppressing a peak power. <P>SOLUTION: This clock generation circuit is provided with: a counter circuit 5 for counting the edge of a reference clock 11, and for generating a timing signal in each of the prescribed number of clock cycles; a bit map circuit 4a for storing bit map information 14a having the number of bits equal to the prescribed number of clock cycles; an intermittent clock generation circuit 2a for generating an intermittent clock 12a as a pulse string for thinning out and intermitting a pulse with combination shown by the bit map information 14a from the reference clock 11, and for outputting it according to a timing signal; a bit map circuit 4b for storing bit map information 14b having the number of bits equal to the prescribed number of clock cycles; and an intermittent clock generation circuit 2b for generating an intermittent clock 12b as a pulse string for thinning out and intermitting the pulse with the combination shown by the bit map information 14b from the reference clock 11, and for outputting it according to the timing signal. <P>COPYRIGHT: (C)2012,JPO&INPIT |
