发明名称 Bit ordering for packetised serial data transmission on an integrated circuit
摘要 An on-chip integrated circuit interconnect 16 uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is selected such that higher priority bits required by a receiving slave device in order that it can commence processing the transaction are sent first. This reduces the latency of the system.
申请公布号 US8045573(B2) 申请公布日期 2011.10.25
申请号 US20060310012 申请日期 2006.08.16
申请人 ARM LIMITED 发明人 MATHEWSON BRUCE JAMES;HARRIS ANTONY JOHN
分类号 H04L12/56;H04J1/16 主分类号 H04L12/56
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