| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for laying out power wiring of a semiconductor device, suppressing increase in size of semiconductor integrated circuits while eliminating substrate noise violations.SOLUTION: The method for laying out a power wiring of the semiconductor integrated circuits mixedly including analog circuits and digital circuits includes steps of: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a maximum current node from nodes of the digital circuit when a substrate noise violation exists in a voltage value of a node of the analog circuit, the maximum current node having a maximum amount of current flowing into the node of the analog circuit; searching a path of a current flowing into the maximum current node in the digital circuit; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor. |
