| 摘要 |
There is provided a pipeline type A/D converter capable of expanding an input range and increasing the number of bits of digital output signals, without increasing thermal noises or an open loop gain needed for an operational amplifier. The number of sample-hold capacitors is divided from M into N and further multiplies the reference voltage by N to increase the number of capacitors available to add to and subtract from the reference voltage. Consequently, it enables expanding the input range and increasing the number of bits of the digital output signals. On this occasion, the thermal noises are not deteriorated before and after the division of the capacitors, as the analog signal is sampled by all the capacitors. Further, the open loop gain needed for the operational amplifier will not be increased, since the ratio of the capacitors each used as a feedback element for amplifying the analog signal to the remaining capacitors is unchanged before and after the division of the capacitors.
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