发明名称 Programmable Drive Strength in Memory Signaling
摘要 Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.
申请公布号 US2011231692(A1) 申请公布日期 2011.09.22
申请号 US20100728101 申请日期 2010.03.19
申请人 LOINAZ MARC 发明人 LOINAZ MARC
分类号 G06F1/04;G06F12/00 主分类号 G06F1/04
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