发明名称 ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To provide a technique for appropriately accessing a DRAM in a system having different data bus widths depending on chip selections. SOLUTION: A standard DRAM 161 is connected with a memory control circuit 150 via a first external bus, and an option DRAM 162 is connected with the memory control circuit 150 via the first external bus and a second external bus. A sum of widths of the first external bus and the second external bus is a times wider than the bus width of the first external bus. When the memory control circuit 150 receives an access request to the option DRAM 162, the memory control circuit 150 issues a command for b times access to the option DRAM 162 to access the option DRAM 162, and when the memory control circuit 150 receives an access request to the standard DRAM 161, the memory control circuit 150 issues a command for a×b times access to the standard DRAM 161 to access the standard DRAM 161. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011186898(A) 申请公布日期 2011.09.22
申请号 JP20100053038 申请日期 2010.03.10
申请人 SEIKO EPSON CORP 发明人 SAITO TAKESHI
分类号 G06F12/06;G06F12/02 主分类号 G06F12/06
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