发明名称 PROCESS FOR FABRICATING A MULTILAYER STRUCTURE WITH POST-GRINDING TRIMMING
摘要 The invention relates to a process for fabricating a multilayer structure (130) comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800 mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 μm in the trimmed region.
申请公布号 US2011230003(A1) 申请公布日期 2011.09.22
申请号 US201113043088 申请日期 2011.03.08
申请人 S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES 发明人 VAUFREDAZ ALEXANDRE;MOLINARI SEBASTIEN
分类号 H01L21/762;H01L31/18 主分类号 H01L21/762
代理机构 代理人
主权项
地址