发明名称 METHOD OF FABRICATING U-GATE TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To provide a non-planar semiconductor transistor structure which improves the short channel performance, and to provide a manufacturing method for the structure. SOLUTION: A U-shaped fin 305 is formed on an insulating layer 301 which resides on a substrate 360; a gate dielectric layer 362 and a gate electrode 363 are formed on one part of the fin; and a source region 403 and a drain region 404 are formed on both sides of the U-shaped fin 305. The gate electrode 363, together with a gate dielectric layer 362, covers a top surface 306 of one part of the U-shaped fin 305, and two sidewalls 307 which reside the opposite position, and a bottom 320 of one part of a recess 319, which resides in the U-shaped fin 305 and opposing two sidewalls 364, and substantially increases the width of the channel region that allows flow of a current. The current/voltage characteristics of a U-shaped transistor structure is controlled by the performance of a corner part of a device, over the entire gate voltage range, and thereby the short-channel effect is suppressed minimally; and a current under a threshold and a drive current are optimized. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011181952(A) 申请公布日期 2011.09.15
申请号 JP20110103293 申请日期 2011.05.02
申请人 INTEL CORP 发明人 DOYLE BRIAN;SINGH SURINDER;SHAH UDAY;BRASK JUSTIN;CHAU ROBERT
分类号 H01L29/786;H01L21/336 主分类号 H01L29/786
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