发明名称 Trojan-Resistant Bus Architecture and Methods
摘要 A method of securing bus architecture from a Trojan attack. A restricted address access detector generates an unauthorized access detection, signal when a master ID signal is within a restricted range. The unauthorized access detection signal disables the requested slave select signal, and the address decoder instead outputs a default slave select signal. A counter determines the duration of a lock signal from a master, and a comparator activates a malicious bus lock signal if the lock signal duration exceeds a threshold. The master mask register forcibly gates the lock signal upon receipt of the malicious bus lock signal. If the duration of a wait request from a slave exceeds a maximum duration register value, a comparator activates a malicious wait detection signal to disable the wait request signal. The method might include storing identifying information about the malicious master and storing a slave ID corresponding to the malicious slave.
申请公布号 US2011225651(A1) 申请公布日期 2011.09.15
申请号 US201113042233 申请日期 2011.03.07
申请人 VILLASENOR JOHN D;KIM LOK WON 发明人 VILLASENOR JOHN D.;KIM LOK WON
分类号 G06F21/00;G06F13/14 主分类号 G06F21/00
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