发明名称 Interface circuit
摘要 An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.
申请公布号 US8018264(B2) 申请公布日期 2011.09.13
申请号 US20100797123 申请日期 2010.06.09
申请人 YAMATAKE CORPORATION 发明人 UENO TATSUYA
分类号 H03K3/02;H03K19/003;H03K19/0175 主分类号 H03K3/02
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