发明名称 Memory device having additional selection transistors and main bit lines
摘要 A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8×N) memory cells arranged in a row direction as a unit to be used as a storage region. The number of a plurality of selection word lines is at least eight, and the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines. At least one selection transistor in addition to (8×N) selection transistors are connected in total to the plurality of selection word lines. A plurality of main bit lines includes at least one main bit line in addition to (4×N) main bit lines connected to the common drain of a pair of selection transistors.
申请公布号 US8013378(B2) 申请公布日期 2011.09.06
申请号 US20080270170 申请日期 2008.11.13
申请人 PANASONIC CORPORATION 发明人 TAKAHASHI KEITA
分类号 H01L27/108 主分类号 H01L27/108
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