发明名称 Updating instructions to free core in multi-core processor with core sequence table indicating linking of thread sequences for processing queued packets
摘要 A method of updating execution instructions of a multi-core processor comprising receiving execution instructions at a processor including multiple programmable processing cores integrated on a single die, selecting subset of at least one of the cores, and loading at least a portion of the execution instructions to the subset of cores and replacing existing execution instructions, associated with the first subset of programmable processing cores, with the received execution instructions while at least one of the other cores continues to process received packets, wherein a sequence of threads provided by the cores sequentially retrieve packets to process from at least one queue, the sequence proceeding from a subsequence of at least one thread of one core to a subsequence of at least one thread on another core and wherein the sequence of threads is specified by data identifying, at least, the next core in the sequence.
申请公布号 US8015392(B2) 申请公布日期 2011.09.06
申请号 US20040954326 申请日期 2004.09.29
申请人 INTEL CORPORATION 发明人 NAIK UDAY;LEE CHING BOON;LIM AI BEE;SAHARA KOJI
分类号 G06F9/46 主分类号 G06F9/46
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