SOURCE FOLLOWER INPUT BUFFER

摘要

An input source follower buffer and biasing circuitry for an analog-to-digital converter (ADC) provides improved linearity. Portions INP, INM of an input signal are input to a biasing circuit 212 and buffers 202-1, 202-2 for sampling by sample-and-hold (S/H) circuits 204-1, 204- 2. Current source 302 provides a current to the drain of NMOS transistor Q8 whose gate receives a bias voltage NCAS and provides a bias voltage NBIASP to the gate of NMOS transistor Q9. Portion INM is provided through capacitor CIN to a node between cascaded transistors Q8, Q9. This enables a signal current to flow from ground through second transistor (Q9) and capacitor CIN. The signal current is mirrored by each NMOS transistor Q5, Q7 and provided to capacitors CBl, CB2. Portion INP is provided to the gates of NMOS transistors Q4, Q6 (which each operate as source followers) and do not generally provide the signal current. The input circuitry is able to supply voltages and currents to S/H circuit 204-1, 204-2 with improved linearity.