| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit design apparatus and method, capable of controlling the number of delay elements to be inserted to solve especially timing constraint violation. SOLUTION: The circuit design apparatus includes: a layout unit 10 for arranging and wiring logical elements based on circuit information 14 having a net list including connection information between logical elements to be used for circuit design and information of delay time of the logical elements, and for generating a layout; a timing analysis unit 11 for detecting existence of timing constraint violation in the layout while referring to the circuit information and layout information 18; a selection unit 12 for selecting an additional delay element to be arranged by referring to the circuit information while going back from an end point of the detected timing constraint violation path up to a start point; and a logical element correction unit 13 which, when determining that the selected additional delay element can be used in common for a plurality of paths in which timing constraint violation is generated, integrates the plurality of paths and arranges the selected additional delay element. COPYRIGHT: (C)2011,JPO&INPIT
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