Single latch data circuit in a multiple level cell non-volatile memory device

摘要

A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.