| 摘要 |
PROBLEM TO BE SOLVED: To provide a control device which reliably recovers any of a plurality of processor cores where a failure occurs. SOLUTION: A sub-core 32 includes: a first operating state monitoring unit 53 which transmits a predetermined command to a main core 31 at predetermined transmission intervals to receive a response to it; a first failure determination unit 54 which determines that a failure has occurred in the main core 31 if no response is received within a predetermined response time; and a first reset instruction unit 55 which, if the occurrence of a failure is determined, issues an instruction for reset after recording an operation log on a nonvolatile memory 23. The main core 31 includes: a second operating state monitoring unit 64 which receives the predetermined command from the sub-core 32 to transmit a response to it; a second failure determination unit 65 which determines that a failure has occurred in the sub-core 32 if no next predetermined command is received within a predetermined reception time; and a second reset instruction unit 66 which, if the occurrence of a failure is determined, issues an instruction for reset after recording an operation log on the nonvolatile memory 23. COPYRIGHT: (C)2011,JPO&INPIT
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