发明名称 Reducing Jitter in a Recovered Data Stream Clock of a Video DisplayPort Receiver
摘要 The system and method, applicable to video display port applications, reduces the jitter in a regenerated data stream clock by using a first-in first-out (FIFO) storage memory to average the variations thereto. The method comprises loading the data extracted from data packets, received over a high speed connection, into the FIFO and running the application using the data in the FIFO. An initial frequency value of the stream clock Fvid is generated from the link clock Flink. Two integer values received over the link, M and N, that establishes a relationship between Flink and Fvid, are used to initiate recovery of Fvid. Lower and upper limits are set for data in the FIFO and the value of Fvid is adjusted to keep the level of data stored in the FIFO within these limits. Accordingly, variations of Fvid are averaged over the limits of the FIFO, thereby reducing the jitter.
申请公布号 US2011193970(A1) 申请公布日期 2011.08.11
申请号 US201113012986 申请日期 2011.01.25
申请人 ANALOGIX SEMICONDUCTOR, INC. 发明人 ZHU NING
分类号 H04N17/00 主分类号 H04N17/00
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