The present invention describes a novel method of fabricating nano-resistors (22) which allows full integration with standard CMOS fabrication process. The resistor comprises long and thin nano-structures as resistive element. It is formed by conductive nano-spacers (18B) on insulating layer. An embodiment of such structure is polysilicon nano-structures doped or implanted with n-type or p-type ions (20) to improve material conductance. The electrical properties of the device will change with respect to the dimension of these nano-structures. Resistors with polysilicon nano-structures down to 10 nm can be produced with resulting measured resistance in the MOhm scale.
申请公布号
WO2011096790(A2)
申请公布日期
2011.08.11
申请号
WO2010MY00317
申请日期
2010.12.13
申请人
MIMOS BERHAD;BIEN, CHIA SHENG DANIEL;AZLINA, MOHD ZAIN;LEE, HING WAH
发明人
BIEN, CHIA SHENG DANIEL;AZLINA, MOHD ZAIN;LEE, HING WAH