发明名称 Clock distribution circuit and layout design method using same
摘要 A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.
申请公布号 US7990179(B2) 申请公布日期 2011.08.02
申请号 US20100778207 申请日期 2010.05.12
申请人 RENESAS ELECTRONICS CORPORATION 发明人 NAKAHASHI TOSHIAKI
分类号 H03K19/096;H03K19/094 主分类号 H03K19/096
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