| 摘要 |
A clock/data recovery circuit comprises a data duty correcting circuit (400) for outputting correction data obtained by correcting the duty of input data according to the level of a correction signal, a clock recovery circuit (100) for generating a recovered clock synchronized with the edge timing of the correction data, a data identifying circuit (200) for identifying the correction data by the recovered clock, and a data duty detecting circuit (300) for detecting the duty of the correction data by the recovered clock and outputting the correction signal indicating a duty correction amount to the data duty correcting circuit. |
