发明名称 |
METHOD AND PROGRAM OF VERIFYING SEMICONDUCTOR DEVICE PATTERN |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method and program of verifying a semiconductor device pattern, with which computational loads can be reduced and computational time can be reduced. <P>SOLUTION: The method of verifying a semiconductor device pattern includes: a first step (ST11) to calculate a mask pattern; a second step (ST12) to calculate the shape of a photoresist formed on a semiconductor substrate; a third step (ST13) to perform uniform resizing using graphic processing and calculate only artificial temporary processing forms; a fourth step (ST14) to graphically verify whether a designing pattern is formed on the semiconductor substrate or not and to detect potentially risky places; and a fifth step (ST15) to simulate processing of the potentially risky places and calculate partial processing forms. <P>COPYRIGHT: (C)2011,JPO&INPIT |
申请公布号 |
JP2011141491(A) |
申请公布日期 |
2011.07.21 |
申请号 |
JP20100003308 |
申请日期 |
2010.01.08 |
申请人 |
TOSHIBA CORP |
发明人 |
NAKAYAMA KOICHI;KOTANI TOSHIYA;KODAMA CHIKAAKI;NAKAJIMA FUMIHARU;MASHITA HIROMITSU;TAGUCHI TAKAFUMI |
分类号 |
G03F1/36;G03F1/68;G03F1/70;G06F17/50;H01L21/027;H01L21/82 |
主分类号 |
G03F1/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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