发明名称 (18, 9) Error correction code for double error correction and triple error detection
摘要 An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: <maths id="MATH-US-00001" num="00001"> <MATH OVERFLOW="SCROLL"> <MROW> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MROW> <MN>3</MN> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> </MROW> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>6</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>12</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MROW> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>7</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> </MROW> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>14</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>11</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>5</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>1</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>2</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>4</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>8</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MROW> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO>⁢</MO> <MI>beta</MI> </MROW> <MN>1</MN> </MUNDER> <MN>16</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>15</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>13</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>9</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MUNDER> <MROW> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO>⁢</MO> <MN>0</MN> </MROW> <MROW> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO>⁢</MO> <MN>1</MN> </MROW> </MUNDER> <MO>⁢</MO> <MSTYLE> <mspace width="1.4em" height="1.4ex"/> </MSTYLE> <MO>⁢</MO> <MSUP> <MUNDER> <MI>beta</MI> <MN>1</MN> </MUNDER> <MN>10</MN> </MSUP> <MO>⁢</MO> <MSTYLE> <mspace width="0.6em" height="0.6ex"/> </MSTYLE> <MO>⁢</MO> <MUNDER> <MN>1</MN> <MROW> <MN>1</MN> <MO>,</MO> </MROW> </MUNDER> </MROW> </MATH> </MATHS> where beta is a root of the polynomial x<SUP>17</SUP>-1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.
申请公布号 US7243293(B2) 申请公布日期 2007.07.10
申请号 US20030744564 申请日期 2003.12.23
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHEN CHIN-LONG
分类号 H03M13/00;H03M13/05 主分类号 H03M13/00
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