发明名称 |
Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy |
摘要 |
A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when column steering redundancy is requested. A plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in an array of memory cells. A second decoder receives the input address and selectively activates a first set of sense amplifiers of the plurality of sense amplifiers and selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated.
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申请公布号 |
US2011164463(A1) |
申请公布日期 |
2011.07.07 |
申请号 |
US20100652345 |
申请日期 |
2010.01.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PILO HAROLD;RAMADURAI VINOD |
分类号 |
G11C29/00;G11C7/02;G11C8/10 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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