| 摘要 |
PROBLEM TO BE SOLVED: To implement an adaptive optimized compare-exchange operation. SOLUTION: Processing logic receives a FASTCMPXCHG operation in the execution pipeline (200). The processing logic then looks for a cache line tag that includes microarchitectural hint bits associated with a FASTCMPXCHG instruction (202). A tag that a preceding CLMARK can utilize is present for each cache line if hardware has a capability of processing a FASTCMPXCHG. If the hardware does not have the tags, then CLMARK and FASTCMPXCHG are not supported. In this case, processing logic then just utilize the [mem], testval, and newval parameters to execute a standard CMPXCHG instruction in place of the listed FASTCMPXCHG instruction in the code (212). COPYRIGHT: (C)2011,JPO&INPIT
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