发明名称 Method for manufacturing a heterostructure with stress minimisation
摘要 <p>The method involves bonding a wafer (110) i.e. silicon or Silicon on insulator (SOI) substrate, to another wafer (120) i.e. sapphire substrate, where the former wafer has the thermal expansion coefficient that is lower than the thermal expansion coefficient of the latter wafer. The former wafer is partially trimmed, so that the former wafer presents the thickness lower or equal to 55 micrometers, at the level of the trimmed portion of the former wafer. The reinforcement of the bond of the wafers is annealed. The trimming step is conducted after the bonding step and before the annealing step.</p>
申请公布号 EP2339615(A1) 申请公布日期 2011.06.29
申请号 EP20100192594 申请日期 2010.11.25
申请人 S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES 发明人 VAUFREDAZ, ALEXANDRE
分类号 H01L21/762 主分类号 H01L21/762
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