发明名称 Multi-bit error correction scheme in multi-level memory storage system
摘要 A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells.
申请公布号 US7966547(B2) 申请公布日期 2011.06.21
申请号 US20070772356 申请日期 2007.07.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LAM CHUNG H.
分类号 G06F11/10;G11C29/00 主分类号 G06F11/10
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