| 摘要 |
Mechanisms for saving power by powering down an instruction fetch array based on capacity history information of an instruction buffer are provided. The mechanisms operate to receive a current access to an instruction buffer of a processor. The current access is a fetch of a group of one or more instructions to be stored in the instruction buffer. A determination is made, for one or more prior accesses occurring prior to the current access, if a predetermined pattern of capacity availability of the instruction buffer indicates that the instruction buffer is likely to have available capacity to store the group of one or more instructions of the current access. An instruction fetch unit array is powered down in response to a determination that the instruction buffer is not likely to have available capacity to store the group of one or more instructions of the current access.
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