发明名称 REDUNDANT BINARY ADDITION DECODING DEVICE AND MULTIPLICATION DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a redundant binary addition decoding device that achieves higher-speed decoding from a redundant binary number to a usual binary number. <P>SOLUTION: The redundant binary addition decoding device which performs redundant binary addition of a plurality of digits and decodes the addition result of the redundant binary addition to usual binary addition. The redundant binary addition decoding device includes a plurality of sub redundant binary addition decoding means corresponding to each digit. Each of the sub redundant binary addition decoding means, based on an augend and an addend, generates a plurality of carry signal candidates to a higher rigid according to the type of a carry signal input from a lower digit, and selects a carry signal to the higher digit from a plurality of types of generated carry signal candidates according to the carry signal input from the lower digit. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011107969(A) 申请公布日期 2011.06.02
申请号 JP20090262161 申请日期 2009.11.17
申请人 NIHON UNIV 发明人 WAKUI FUMIO;ASAKAWA MITSUHIRO
分类号 G06F7/50;G06F7/523 主分类号 G06F7/50
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