发明名称 LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL
摘要 PROBLEM TO BE SOLVED: To supply information about a fill level of first-in-first-out (FIFO) and/or a write status of FIFO to a sending or source domain. SOLUTION: Data from a source domain operating at a first data rate are transferred to a FIFO in another domain operating at a different data rate. A source side counter tracks space available in the FIFO. The initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain. The counter increments in response to signaling from the sink domain of a read of data from the FIFO. The source may send one more beat of data when the counter indicates the FIFO is full, and the last beat of data is continuously sent from the source until it is indicated that a FIFO position became available, thereby effectively providing one more FIFO position. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011101390(A) 申请公布日期 2011.05.19
申请号 JP20100274455 申请日期 2010.12.09
申请人 QUALCOMM INC 发明人 DOCKSER KENNETH ALAN;AUGSBURG VICTOR ROBERTS;DIEFFENDERFER JAMES NORRIS;BRIDGES JEFFREY TODD;CLANCY ROBERT DOUGLAS;SARTORIUS THOMAS ANDREW
分类号 H04L13/08;G06F13/38 主分类号 H04L13/08
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