发明名称 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
摘要 |
PROBLEM TO BE SOLVED: To reduce a variation of a characteristic of a semiconductor device having an n-type MIS transistor. SOLUTION: A memory n-type MIS transistor QM1 formed in a memory region RM on a silicon substrate 1 has a memory source-drain region SD1 including a memory extension regions LD1 formed below both side walls of a memory gate electrode GE1. A logic n-type MIS transistor QL1 formed in the logic region RL has a logic source-drain region SD2 including logic extension regions LD2 formed below both side walls of the logic gate electrode GE2. The atomic weight of the n-type impurity of the memory extension region LD1 is smaller than the atomic weight of the n-type impurity of the logic extension region LD2. The memory n-type MIS transistor QM1 has a channel area smaller than that of the logic n-type MIS transistor QL1. COPYRIGHT: (C)2011,JPO&INPIT
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申请公布号 |
JP2011082461(A) |
申请公布日期 |
2011.04.21 |
申请号 |
JP20090235657 |
申请日期 |
2009.10.09 |
申请人 |
RENESAS ELECTRONICS CORP |
发明人 |
NISHIDA AKIO;TSUNOMURA TAKAAKI |
分类号 |
H01L27/088;H01L21/8234;H01L21/8244;H01L27/10;H01L27/11;H01L29/417;H01L29/423;H01L29/49 |
主分类号 |
H01L27/088 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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