| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock signal amplification circuit that suppresses jitter and can operate at a high speed, and to provide a method of controlling the same. <P>SOLUTION: The clock signal amplification circuit includes an amplification circuit 11, a first switch 12, and a second switch 13. The amplification circuit 11 amplifies a clock signal. The first switch controls the on/off of the amplification circuit 11 according to a selection signal SEL and the second switch 13 opens/closes complementarily with respect to the first switch 12 according to the selection signal SEL. Test clock signals TST and TSTB used for a test mode operation are input into the amplification circuit 11 via the second switch 13. The amplification circuit 11 outputs a signal obtained by amplifying input signals IN and INB that are clock signals or the test clock signals TST and TSTB, according to the selection signal SEL. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
