Method and device for testing TSVs in a 3D chip stack

摘要

A 3D chip stack comprises at least a first die (20) comprising a first electrical circuit and a second die (21) comprising a second electrical circuit. The first die (20) furthermore comprises at least one first through-substrate via (22) for providing electrical connection between the first electrical circuit in the first die (20) and the second electrical circuit in the second die (21), test circuitry (23) and at least one second through-substrate via (24) electrically connected between the at least one first through-substrate via (22) and the test circuitry (23). The electrical connection between the at least one first through-substrate via (22) and the at least one second through-substrate via (24) is made outside the second die (21). This shows the advantage that it is possible to test the at least one through-substrate via (22) in the first die (20) even if the second die (21) is not provided with dedicated test circuitry.