| 摘要 |
Data processing system including a processor (100), data memory (132), program memory (134) and principal bus (110) common to data and program memories and connecting them to the processor. The system includes a distribution interface (120) between the principal bus (110) and the memories to alternatively put then in communication, via the principal bus, in an 'active' access mode and to maintain the other memory in 'passive' access mode authorizing subsequent rapid access. The distribution interface includes a copier (122) for transferring signals between the principal bus (110) and a first secondary bus (140) connecting the interface to the data memory, and a second secondary bus (150) connecting the interface to the program memory. The interface includes a memory (125) to conserve the logic state of a signal applied to a memory at the moment of its passage from an active access mode, when it is communication with the processor, to a passive access mode. The principal bus includes a data bus (112), an address bus (114), a control bus (116) and an access indication bus (118). |
