发明名称 SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBSTRATES
摘要 A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.
申请公布号 US2011045659(A1) 申请公布日期 2011.02.24
申请号 US20100915557 申请日期 2010.10.29
申请人 INTEL CORPORATION 发明人 HUDAIT MANTU K.;SHAHEEN MOHAMAD A.;LOUBYCHEV DMITRI;LIU AMY W. K.;FASTENAU JOEL M.
分类号 H01L21/20 主分类号 H01L21/20
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