发明名称 Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Ceterain Shared Memory Multi-Processor Systems
摘要 Certain embodiments of the present invention arc directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.
申请公布号 US2011047310(A1) 申请公布日期 2011.02.24
申请号 US20080988459 申请日期 2008.04.28
申请人 BONOLA THOMAS J 发明人 BONOLA THOMAS J.
分类号 G06F13/24 主分类号 G06F13/24
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