发明名称 Apparatus and Method for Memory Management and Efficient Data Processing
摘要 Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
申请公布号 US2011040947(A1) 申请公布日期 2011.02.17
申请号 US20090540756 申请日期 2009.08.13
申请人 KOHLENZ MATHIAS;MIR IDREAS;KHAN IRFAN ANWAR;MADHUSUDAN SATHYANARAYANAN;MAHESHWARI SHAILESH;KRISHNAMOORTHY SRIVIDHYA;URGAONKAR SANDEEP;KLINGENBRUNN THOMAS;LIOU TIM TYNGHUEI 发明人 KOHLENZ MATHIAS;MIR IDREAS;KHAN IRFAN ANWAR;MADHUSUDAN SATHYANARAYANAN;MAHESHWARI SHAILESH;KRISHNAMOORTHY SRIVIDHYA;URGAONKAR SANDEEP;KLINGENBRUNN THOMAS;LIOU TIM TYNGHUEI
分类号 G06F12/02;G06F12/00 主分类号 G06F12/02
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